- Design of High Speed Hardware Efficient 4-Bit SFQ Multiplier
- Design and Synthesis of QPSK
- Design of Multi Value Logic Using Quantum Dot Gate FET
- Design and Simulation of FFT Processor Using Radix-4 Algorithm Using FPGA
- An Area-Efficient Universal Cryptography Processor for Smart Cards
- A High-Speed/Low-Power Multiplier using Spurious Power Suppression Technique
- 3D Lifting based Discrete Wavelet Transform
- A Lossless Data Compression and Decompression Algorithm and Its Hardware Architectur
- Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks
- An Efficient VLSI Architecture for Removal of Impulse Noise in Image
- A Processor-In-Memory Architecture for Multimedia Compression
- A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
- Implementation of Low Power and High Speed Multiplier-Accumulator Using SPST Adder and Verilog
- Design and VLSI Implementation of Anti-collision Enabled Robot Processor Using RFID Technology
- Design and Implementation of 32 – bit RISC Processor
- VHDL Model of Smart Sensor
- Fuzzy based PID Controller using VHDL for Transportation Application
- Implementation of Bus Bridge between AHB and OCP
- Design of Control Area Network Protocol
- DMA Controller for AMBA Bus IP Core
- High Precision Stepper Motor Controller Implementation on FPGA
- Design and Modeling of I2C Bus Controller
- Design and Implementation of CPLD based Solar Power Saving System
- Designing Fuzzy Based Mobile Robot Controller using VHDL
- Design and Implementation of a Real-time Traffic Light Control System
- FPGA Based Digital Space Vector PWM Three Phase Voltage Source Inverter
- Performance Evaluation of Complex Multiplier Using Advance Algorithm
- A Highly linear CMOS Gm-C Low Pass Filter for Mobile Communication
- Design of High Throughput DCT Core Design by Efficient Computation Mechanism
- Low Power QVCO using Adiabatic Logic
- Low Power Adaptive Viterbi Decoder Design for Trellis Coded Modulation
- Adiabatic Technique for Power Efficient Logic Circuit Design
- Advanced Encryption System to Improvise the System Computing Speed
- AMBA-Advanced High Performance Bus IP Block
- A Multichannel Multimode RF Transceiver with DSM
- Asynchronous Transfer Mode Knockout Switch Concentrator
- Behavioral Synthesis of Asynchronous Circuits
- Building an AMBA AHB Compliant Memory Controller
- Implementation of Carry Tree Adder
- Fixed Angle of Rotation Using CORDIC Designs
- Design of FPGA based 32-bit Floating Point Arithmetic Unit
- Design and Synthesis of a Field Programmable CRC Circuit Architecture
- Design of an On-Chip Permutation Network for Multiprocessor SOC
- VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design
- Design and Implementation of Efficient Systolic Array Architecture
- VHDL Environment for Floating Point Arithmetic Logic Unit
- Design and Implementation of High Speed DDR SDRAM Controller
- Design of Phase Frequency Detector and Charge Pump for High Frequency PLL
- Design of Cache Memory with Cache Controller Using VHDL
- An On Chip Design for Prepaid Electricity Billing System
- High Speed Network Devices Using SRL16 Reconfigurable Content Addressable Memory (RCAM)
- IP-SRAM Architecture at Deep Submicron CMOS Technology
- Glitch free NAND based Digitally Controlled Delay Line for Spread Spectrum Clock Generator
- Performance Analysis of Different Bit Carry Look Ahead Adder Using VHDL Environment
- High speed VLSI implementation of 256-bit Parallel Prefix Adders
- FPGA Implementation of Mutual Authentication Protocol using Modular Arithmetic
- Design of Data Link Layer using Wi-Fi MAC Protocols
- Implementation of Overlap based Logic cell and Its Power Analysis
- Low Power 3-2 and 4-2 Adder Compressors Implemented Using ASTRAN
- FPGA Implementation of UTMI and Protocol Layer for USB 2.0
- Review of 5 stage Pipelined Architecture of 8-Bit Pico Processor
- Design of On-Chip Bus OCP Protocol with Bus Functionalities
- FPGA Implementation of Controller Design for Remote Sensing Systems
- Test Pattern Generation Using BIST Schemes
- A Design Technique for Faster Dadda Multiplier
- An Efficient Retouched Bloom Filter Based Word-Matching Stage Of BLASTN
- VLSI Implementation of Single Cycle Access Structure for Logic Test in FPGA Technology
- Design of accumulator Based 3-Weight Pattern Generation using LP-LSFR
- Sleepy Stack Approach Based Low Power Flip Flop
- Low Power High Performance Double Tail Comparator
- Design of a Low Drop-Out Voltage Regulator using VLSI
- VLSI Architecture of Arithmetic Coder Used in SPIHT
- FPGA Based ECG Signal Noise Suppression
- Low Power and High Speed Conditional Push-Pull Pulsed Latches
- An Enhanced Low Cost High Performance Image Scaling Processor Using VLSI
- Design of Finite Impulse Response Filter Using Distributed Arithmetic of Lookup Table
- Pipelined Radix-2k Feedforward FFT Architectures
- Performance Analysis of High Efficiency Low Density Parity-Check Code Decoder for Low Power Applications
- VLSI Implementation of Discrete Wavelet Transform (DWT) for Image Compression
- Implementation of OFDM System using IFFT and FFT
- Design and Implementation of Hamming Code on FPGA using Verilog
- Gabor Filter for Fingerprint Recognition using Verilog HDL
- Floating Point Fused Add-Subtract and Fused Dot-Product Units
- Improvement of the Orthogonal Code Convolution Capabilities using FPGA Implementation
- Design of Non-Volatile Memory Based On Improved Writing Circuit STT-MRAM Technique
- Address Remapping in Arithmetic Functions using ROM Based Approximation Approaches
- Design of Flip-Flops for High Performance VLSI Applications using Deep Submicron CMOS Technology
- Low Power H.264 Video Compression Architecture for Mobile Communication
- Enhanced Scan in Low Power Scan Testing
- Power Gating Implementation for Noise Mitigation with Body-Tied Triple-Well Structure
- VHDL Implementation of Universal Asynchronous Receiver Transmitter
- Design and ASIC Implementation of a 3GPP LTE Advance Turbo Encoder and Turbo Decoder
- Design of Low Power Multiplier using Compound Constant Delay Logic Style
- Design of Flash ADC using Improved Comparator Scheme
- High Performance Flash Storage System Based on Virtual Memory and Write Buffer
- An Effective Leading Zero Anticipation for High Speed Floating Point Addition and Subtraction
- FPGA Implementation of an LFSR based Pseudorandom Pattern Generator for MEMS Testing
- Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST Implemented in HDL
- Design and Implementation of Vending Machine using Verilog HDL
- High-Speed Low-Complexity Reed-Solomon Decoder
- FM Radio Receiver with Digital Demodulation
- Implementation of High-Speed Pipeline VLSI Architectures
Click Here- Solar Based Projects
